Lab Architecture of the Elaborators
From Boolean logic to CPU pipelining: ALU, registers, memory, cache, MIPS/RISC-V assembly. Revised by the UniTO course (270 hours of audio transcribed).
Prerequisites
- Discrete Math Basics
- Elementary programming
What you'll learn
- Understanding a CPU MIPS data path
- Write programs in RISC-V Assembly Language
- Cache Hit/Miss Rate Analysis
- Understand Pipelining and Hazard